FSMs, Synchronous Digital Systems¶
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FSM: Finite State Machine¶
state transition diagram¶
- s0 初始状态；input/output；箭头指向是 next state
clock and registers¶
Flip-Flop¶
- 时钟上升沿；Q = D，其余时刻什么也不做
register delay¶
- clk-to-q delay
- Registers can’t transfer the D input to Q output instantly
- clk-to-q delay: Time it takes after the rising edge for the Q output to change
register constraints¶
setup time¶
- Setup time: Time before rising edge when the D input must be stable
hold time¶
- D input cannot change before this, so the register can read a stable value.
maximizing clock frequency¶
-
Clock period ≥ clk-to-q delay + longest combinational delay + setup time -
Hold time ≤ clk-to-q delay + shortest combinational delay